期末考

module top; system_clock #800 clock1(A); system_clock #400 clock1(B); system_clock #200 clock1(C); system_clock #100 clock1(D); number n1(F,A,B,C,D); endmodule module number(F,A,B,C,D); input A,B,C,D; output F; wire A1,B1,C1,D1,w1,w2,w3,w4; not(A1,A); not(B1,B); not(C1,C); not(D1,D); and(w1,A1,C1); and(w2,A,B1,D1); and(w3,A,B,C); and(w4,B1,C1,D1); or(F,w1,w2,w3,w4); endmodule module system_clock(clk); parameter PERIOD=100; output clk; reg clk; initial clk=0; always begin #(PERIOD/2)clk=~clk; end always@(posedge clk) if($time>1000) $stop; endmodule