2014年5月29日 星期四
期末考
module top;
system_clock #800 clock1(A);
system_clock #400 clock1(B);
system_clock #200 clock1(C);
system_clock #100 clock1(D);
number n1(F,A,B,C,D);
endmodule
module number(F,A,B,C,D);
input A,B,C,D;
output F;
wire A1,B1,C1,D1,w1,w2,w3,w4;
not(A1,A);
not(B1,B);
not(C1,C);
not(D1,D);
and(w1,A1,C1);
and(w2,A,B1,D1);
and(w3,A,B,C);
and(w4,B1,C1,D1);
or(F,w1,w2,w3,w4);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
2014年4月17日 星期四
一位元加法器
reg a,b;
reg carry_in ;
wire sum;
wire carry_out;
adder1_behavorial A1(carry_out, sum, a, b, carry_in);
initial
begin
carry_in = 0; a = 0; b = 0;
# 100 if ( carry_in != 0 | sum !== 0)
$display(" 0+0+0=00 sum is WRONG!");
else
$display(" 0+0+0=00 sum is RIGHT!");
carry_in = 0; a = 0; b = 1;
# 100 if ( carry_in != 0 | sum !== 1)
$display(" 0+0+1=01 sum is WRONG!");
else
$display(" 0+0+1=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 0;
# 100 if ( carry_in != 0 | sum !== 1)
$display(" 0+1+0=1 sum is WRONG!");
else
$display(" 0+1+0=01 sum is RIGHT!");
carry_in = 0; a = 1; b = 1;
# 100 if ( carry_in != 1 | sum !== 0)
$display(" 0+1+1=10 sum is WRONG!");
else
$display(" 0+1+1=00 sum is RIGHT!");
carry_in = 1; a = 0; b = 0;
# 100 if ( carry_in != 0 | sum !== 1)
$display(" 1+0+0=01 sum is WRONG!");
else
$display(" 1+0+0=01 sum is RIGHT!");
carry_in = 1; a = 0; b = 1;
# 100 if ( carry_in != 1 | sum !== 0)
$display(" 1+0+1=10 sum is WRONG!");
else
$display(" 1+0+1=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 0;
# 100 if ( carry_in != 1 | sum !== 0)
$display(" 1+1+0=10 sum is WRONG!");
else
$display(" 1+1+0=10 sum is RIGHT!");
carry_in = 1; a = 1; b = 1;
# 100 if ( carry_in != 1 | sum !== 1)
$display(" 1+1+1=11 sum is WRONG!");
else
$display(" 1+1+1=11 sum is RIGHT!");
$finish;
end
endmodule
module adder1_behavorial (carry_out, sum, a, b, carry_in);
input a, b, carry_in;
output carry_out, sum;
assign sum = (~a&b&~carry_in)|(~carry_in&a&~b)|(~a&~b&carry_in)|(a&b&carry_in);
assign carry_out = a&carry_in|a&b|b&carry_in;
endmodule
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